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The Trading Mesh

Picking the right memory for your FPGA trading platform

Tue, 17 Feb 2015 11:25:59 GMT           

By: Abhimanyu Vyas, Cypress Semiconductors

The last few years in algo-trading markets have seen the development of lower-latency solutions using custom hardware like FPGA solutions. FPGAs provide vast concurrent resources which can be configured to drastically reduce round trip trade latency compared to software based solutions. They are programmed to be self sufficient to process applications like data acquisition, risk matching and order processing. With Altera Arria-10 and Xilinx Ultrascale around the corner, the processing capabilities of FPGAs will see a drastic enhancement. However, a key bottleneck for implementing these trading strategies on FPGA will be the performance of memory. As the input stream of stock data from exchange is not received in a deterministic sequential manner, the memory access for implementing trading strategy is also random. Using traditional DRAM for such fast random accesses leads to huge penalties because they are optimized for sequential access involving deterministic computation algorithms. QDR SRAM memories on the other hand are built for small bursts of random accesses and can enable FPGA solutions to drastically lower the overall tick to trade latency.

Most FPGA based trading solutions use external memory for maintaining order books and data for time stamp logging for risk analysis. Both of these data tables need to be continuously updated based on the feed received from the exchange. The memory access needed for these table updates involves small data bursts and quick data retrieval with minimum latency penalty.  In the memory parlance, this random access rate of a memory is measured in terms of a metric called Random Transaction Rate (RTR). RTR represents the number of random read or write accesses that a memory can support in a given time. It is measured in multiples of transactions per second (for example, MT/s or GT/s).

The most critical factor in determining the RTR and the latency penalty involved with the memory device is the core memory technology; for example, synchronous DRAM (SDRAM), reduced latency DRAM (RLDRAM), or QDR® Synchronous SRAM (QDR SRAM). In SDRAM and RLDRAM, true random access is largely limited by random cycle time latency (tRC). The maximum RTR is approximately the inverse of tRC (1/tRC). SDRAM tRC has not evolved substantially over the past 10 years (nor is it expected to evolve going forward) and stands at ~48 ns, which correlates to a 21 MT/s RTR. Other DRAM-based memory devices have been designed to improve tRC at the expense of density. For example, RLDRAM 3 has a tRC of 8 ns, which correlates to a 125-MT/s RTR. QDR SRAM is specifically optimized for random access. The latest QDR SRAM, QDR-IV family delivers a 2133-MT/s RTR with a latency of 7.5ns.The table below provides a comparison of QDR® memories with other core memory technology solutions.






Read Latency

7.5 ns

4.5 ns

8 ns

47.6 ns

Max. RTR(MT/s)





Max. Frequency

1,066 MHz

550 MHz

1066 MHz

2132 MHz

Max. Density





I/O Ports

2 R/W

1 R + 1 W

1 R + 1 W

1 R + 1 W

Although DRAM based memories offer high memory capacity, they fail to meet the latency and performance needed for trading platforms. Due to these inherent advantages of QDR memories, many vendors are adopting QDR memory solutions including QDR-IV for their next generation trading solutions. This places them at an early mover advantage over customers using other slower memory solutions. 

For more details on QDR memories refer to the QDR consortium website and QDR-IV website at


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